1. Field of the Invention
The present invention relates generally to semiconductor circuitry. More particularly, the present invention relates to a charge pump circuit usable in a semiconductor.
2. Description of Related Art
High voltage generators using charge pump circuits have been widely used in various semiconductor products. These high voltage generators are used for generating programming or erasing voltage for non-volatile memory having floating gate devices, such as EPROM, EEPROM, or Flash EEPROM. The high voltage generator may also be used for RAM devices such as DRAM, SRAM, or FeRAM in order to boost word line voltage.
FIG. 1(a) is the conventional charge pump circuit with four stages, disclosed in publication of IEEE Journal of Solid State Circuit, Vol. 11, pp. 374-378, June 1976, which is incorporated herein by reference in its entirety. Unit gain stage consists of NMOS switch(N1xcx9cN4) and pumping capacitor(C1xcx9cC4). The bulk of NMOSFETs are biased by constant voltage such as ground potential. Series connection of plurality of unit gain stage from node of supply voltage (Vdd) to output node forms the charge pump circuit. As shown in FIG. 1(b), input pulses of the charge pump, CLK1 and CLK2, should be non-overlapped pulses having the complementary phase. One drawback of the conventional circuit in FIG. 1(a) is that the gain is limited by an increment of the threshold voltage due to body effects. The gain of a stage is about Vddxe2x88x92Vtn, where Vdd is the supply voltage and Vtn is the threshold voltage of a NMOSFET in the nth stage. Since the bulk potential is biased by constant voltage, the reverse biased voltage between source and bulk(VBS) is increased according to charge up of source node. Since the threshold voltage of nMOSFET is increased with VBS due to the body effects, the threshold voltage of NMOSFET is increased according to an increment of the output voltage. If the Vdd is lower than Vtn, the gain is zero. This circuit needs a pre-charge transistor(N0) between the node of Vdd and the first stage of pump. The pre-charge transistor between Vdd and the first stage is also caused by additional threshold voltage drop.
To overcome the limitations of the conventional charge pump, a variety of modified circuits have been reported in the relevant art. The approach to overcome the voltage loss due to threshold voltage drop is by boosting the gate voltage of pass transistors by incorporating additional gate boosting capacitors and charge-up transistors. The conventional charge pump circuit having a unit stage, which consists of two NMOSFETs and two capacitors is disclosed in the IEEE Journal of Solid State Circuit, Vol. 27, pp. 1540-1545, November, 1992, which is incorporated herein by reference in its entirety. FIG. 2(a) shows the conventional high voltage generator using two NMOS switches one for pass transistor (Np1xcx9cNp4) and the other for gate boosting transistor (NB1xcx9cNb4) with gate boosting capacitor (CB1xcx9cCB4). The pump is controlled by four clock-pulses having two basic complementary phases with several non-overlapped timing margins.
FIG. 2(b) shows the control clocks for the conventional circuit of FIG. 2(a). The amplitude of the clocks is the same as the supply voltage (Vdd). CLK2 and CLK4 are inputs of gate capacitors, where the gate voltage boosted by these input-clocks controls the pass transistors to control whether these are ON or OFF. CLK1 and CLK3 are input pulses to pumping capacitors (CP1xcx9cCP4). In FIG. 2(b), the following timing margins are critical for proper operation. The duration of Tp2 and Tp4 is the time for turning on the pass transistor for transferring charge to the next stage. The margin of T14r, T14f, T23r, and T23f is inhibiting timing margin of turning on the pass transistors to prevent reverse charge flow from output to input direction. T13 is the timing margin for pre-charging gate boosting capacitors (CB1xcx9cCB4). The gate boosting capacitor is pre-charged when the gate voltage of the gate boosting transistor is high while the input clock of the gate boosting capacitor is low and the voltage of the input port is high (timing represented by T13 in the FIG. 2(b). When the input pulse of the gate boosting capacitor is high, the high level of the gate voltage becomes
Vpc+xcex1*Vddxe2x80x83xe2x80x83(1) 
where Vpc is a value of pre-charged voltage and xcex1 is the coupling coefficient between the gate boosting capacitor and the parasitic capacitance of the gate node of pass transistors. The value of xcex1 is obtained as:
xcex1=CB/(CB+Cparag),xe2x80x83xe2x80x83(2) 
where CB is the capacitance of the gate boosting capacitor and Cparag is the parasitic capacitance of the gate node of the pass transistors. The voltage over-drive of the gate node of the pass transistor upon the pre-charged level is about xe2x80x9cxcex1* Vdd.xe2x80x9d The peak level of charge pumping capacitor is:
Vpc+xcex2*Vdd.xe2x80x83xe2x80x83(3) 
where xcex2 is the coupling coefficient between the charge pumping capacitor and the parasitic capacitance of the drain node of the pass transistors. The value of xcex2 is obtained as:
xcex2=CP/(CP+Cparad),xe2x80x83xe2x80x83(4) 
where CP is the capacitance of the charge pumping capacitor and Cparad is the parasitic capacitance of the drain node of the pass transistors. The gate voltage of the pass transistor during charge transfer is maintained at a level about xcex1Vdd is higher than its pre-charged level.
The unit gain of stage n is about Vddxe2x88x92Vtn, so the gain restriction is the same as the conventional circuit shown in FIG. 1(a), where Vtn is the threshold voltage of the pass transistor in the nth stage of the pump. This charge pump circuit can operate only when xcex1Vdd is larger than Vtn. The efficiency is improved compared to the conventional circuit in FIG. 1(a), but the efficiency is still very low.
The drawbacks of the conventional charge pump circuit depicted in FIG. 2(a) are as follows:
1) There is limitation of voltage gain due to body effects. Since NMOSFETs are biased by constant voltage, the threshold voltage is increased as the source voltage is increased.
2) The timing margins of T14f, T14r, T23r and T23f are required to prevent charge flow to reverse direction because the switch on the input side has to be in OFF state before the pumping pulse goes to the high state. The timing margin of T13 and T31, overlapping margins between two pulses, are also necessary to pre-charge the gate boosting capacitors. Therefore, net time for charge transferring operation is limited. And it is very difficult to operate the pump in the high frequencies.
3) High voltage is applied on the gate electrodes of the pass transistors. According to the Equation (1), the maximum voltage across the gate oxide is about Vpc+xcex1*Vdd for transferring the voltage amount of xe2x80x9cVpc+xcex2*Vddxe2x88x92Vthnxe2x80x9d to the capacitor of the next stage at the source side. As the MOS devices scaling down the dielectric thickness of gate oxide become thinner and thinner, the large voltage across the gate oxide may cause reliability problems such as dielectric breakdown, leakage current, and hot carrier effects, etc.
4) This charge pump circuit needs a termination switch between the end of the stage and the output node as represented by NP0 in FIG. 2(a). Since the output node has the highest potential among the circuits, the threshold voltage of this termination nNMOSFET is the most severe.
To overcome the threshold voltage drop due to the body effects of NMOS switches, a charge pump circuit with PMOSFETs on floating wells was disclosed in the U.S. Pat. No. 5,986,947, which is incorporated herein by reference in its entirety. FIG. 3 shows the conventional charge pump circuit using PMOSFETs. Unit stage comprises one pumping capacitor (CP1xcx9cCP4) and one PMOS switch (MP1xcx9cMPN) on floating wells. The input pulses shown in FIG. 1(a) can be used for this circuit. Since the wells are electrically floated, the potential of the well is changing with the source potential of pass transistors. There is no increment of reverse bias between the source and bulk of MOSFETs according to the increment of output voltages. Unit stage gain is approximately Vddxe2x88x92|Vth0|, where |Vth0| is an absolute value of threshold voltage without back bias. The conventional circuit has the following drawbacks:
1) The unit stage gain is xe2x80x9cVddxe2x88x92|Vth0|.xe2x80x9d There is still gain loss due to the threshold voltage of the pass transistors. If Vdd is 1.0 volts and Vth0 is xe2x88x920.5 volts, the unit gain is about 0.5 volts, so that more than twenty stages of pump are needed to generate 10 volts. The increased number of stages causes an increment of the rise time and decrement of the current driving capability.
2) As the pumping capacitor is charged up, the conductance of the PMOS pass transistors is decreased because of an increment of the gate voltage. So, the current derivability of the pump is self-limited during pre-charging operation. To compensate for the loss of conductance, the area of the pumping capacitor and the transfer transistor has to be increased.
3) This circuit needs a transfer switch for termination of the gain stage between the last stage and the output node of the pump. It causes an additional voltage drop and an increment of the rise time to steady the state of the high voltage generator.
In a first aspect of the present invention, a multi-stage charge pump circuit with a particular structure for at least one of the stages is presented. The stage has two switches of which the second switch has a pair of conduction terminals connected between the first control terminal of the first switch and a next stage. The second switch, for instance a transistor, has a second control terminal and the second control terminal is connected to the previous stage. The proposed charge pump circuit is especially suited for use in an integrated memory device. No special last or output stage is required. Further, the circuit is suited for exploiting the floating well-type technology, which is an advantage as the bulk effect is reduced by using such technology.
In a second aspect of the invention, the choice of the steering signals (control and node clocks), possibly due to the selecting of the particular stage structure, is discussed. The selected structure results in less interclock constraints, more in particular in the vanishing of the node clocks constraint, enabling simpler clock design.